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Sung-Yun Lee

M.S.-Ph.D. Candidate

Education

M.S.-Ph.D. in Electrical Engineering

Pohang University of Science and Technology (POSTECH)
2018 - 2024

B.Sc. in Electrical Engineering

Pohang University of Science and Technology (POSTECH)
2014 - 2018

Languages

  • Korean (Native)
  • English (Professional)

Interests

  • VLSI physical design optimization
  • Design technology co-optimization
  • AI in EDA

Career Profile

    Sung-Yun Lee received a B.S. degree in electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, South Korea, in 2018. He received a Ph.D. degree at the CAD and SoC Design Laboratory in Pohang University of Science and Technology (POSTECH), Pohang, South Korea, in 2024. His research interests include VLSI physical design optimization, design technology co-optimization, and machine learning & reinforcement learning on EDA.

Experiences

    Ph.D. Graduate Student Researcher

    Sep. 2018 - Aug. 2024
    Pohang University of Science and Technology (POSTECH)

    – CAD & SoC Design Lab. (Advisor: Seokhyeong Kang)

    Research Internship in Design Technology Team

    Jul. 2022 - Sep. 2022
    Samsung Electronics

    Peer Review Experience

    – IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2023 -)

    Teaching Assistant (TA)

    Pohang University of Science and Technology (POSTECH)

    – [EECE667] VLSI analysis & design software (2021)

    – [PSEP501] Introduction of semiconductor engineering (2020)

    – [EECE276] Electronics & electrical engineering lab I (2019 - 2020)

    – [EECE273] Digital system design (2018)

    Undergraduate Student Researcher

    Pohang University of Science and Technology (POSTECH)

    – CAD & SoC Design Lab. (Apr. 2018 - Aug. 2018)

    – Energy System Lab. (Nov. 2017 - Feb. 2018)

    – Postech Integrated Circuits and Systems Lab. (Dec. 2016 - Feb. 2017)

Projects

  1. Machine Learning Based Electronic Design Automation Software - Samsung Electronics, 2022 - 2024
  2. Software Systems for AI Semiconductor Design - Institute for Information & Communication Technology Planning & Evaluation (IITP), 2021 - 2024
  3. Physical design (place & route) optimization - Samsung Electronics, 2018 - 2023
  4. Block Standard Cell Usage Aware Virtual Netlist Development - Samsung Electronics, 2021 - 2022
  5. Wafer-Scale Deep Learning Accelerator Placement - 2020 ISPD contest organized by Cerebras Systems, 2020
  6. LEF/DEF Based Open-Source Global Router - 2019 ICCAD CAD contest organized by Mentor Graphics & University of California San Diego, 2019
  7. Initial Detailed Routing Contest - 2019 ISPD contest organized by Cadence Design Systems, 2019
  8. Obstacle Avoiding Topology-aware Bus Router - 2018 ICCAD CAD contest organized by Synopsys Taiwan Co., Ltd., 2018
  9. Nano Material Technology Development Program - National Research Foundation of Korea (NRF), 2018

International Journals

  1. Construction of Realistic Place-and-route Benchmarks for Machine Learning Applications
    Daeyeon Kim, Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023
  2. A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
    Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
    IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2020
  3. Additive Statistical Leakage Analysis Using Exponential Mixture Model
    Hyeonjeong Kwon, Sung-Yun Lee, Younghwan Kim, Seokhyeong Kang
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020
  4. Compact Topology-aware Bus Routing for Design Regularity
    Daeyeon Kim, Sanggi Do, Sung-Yun Lee, Seokhyeong Kang
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019

International Conferences

  1. RL-Fill: Timing-Aware Fill Insertion Using Reinforcement Learning
    Jinoh Cho, Seonghyeon Park, Jakang Lee, Sung-Yun Lee, Jinmo Ahn, Seokhyeong Kang
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024
  2. CTRL-B: Back-End-Of-Line Configuration Pathfinding using Cross-Technology Transferable Reinforcement Learning
    Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
    IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition (DATE), 2024
  3. ClusterNet: Routing Congestion Prediction and Optimization using Netlist Clustering and Graph Neural Networks
    Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023
  4. RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization
    Sung-Yun Lee, Seonghyeon Park, Daeyeon Kim, Minjae Kim, Tuyen P. Le, Seokhyeong Kang
    IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition (DATE), 2023
  5. Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration
    Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang
    IEEE/ACM Asia and South Pacific Automation Conference (ASP-DAC), 2022
  6. Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator
    Daeyeon Kim, Hyunjeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang
    IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition (DATE), 2021
  7. Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm
    Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang
    IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
  8. Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
    Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
    IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Awards

  1. Honorable mention in ISPD-2020 contest 'Wafer-Scale Deep Learning Accelerator Placement', 2020
    Minhyuk Kweon, Sunghye Park, Jongho Yoon, Daeyeon Kim, Sung-Yun Lee, Seokhyeong Kang
    Organized by Cerebras Systems
  2. Third place award in ISPD-2019 contest 'Initial Detailed Routing Contest', 2019
    Team Kim&Lee ― Daeyeon Kim, Sung-Yun Lee, Minhyuk Kweon, Seokhyeong Kang
    Organized by Cadence Design Systems
  3. Third place award in ICCAD-2019 CAD contest 'LEF/DEF Based Open-Source Global Router', 2019
    Team PosGRouter ― Daeyeon Kim, Sung-Yun Lee, Seokhyeong Kang
    Organized by Mentor Graphics & University of California San Diego
  4. Best paper award in IEIE SoC Conference, 2019
    Sunghye Park, Sunmean Kim, Sung-Yun Lee, Seokhyeong Kang
    Organized by The Institute of Electronics and Information Engineers

Patents

  1. TERNARY LOGIC CIRCUIT DEVICE
    Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
    US & KR (Registered)
  2. TERNARY LOGIC CIRCUIT DEVICE
    Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
    US & KR (Registered)
  3. APPARATUS FOR LOW POWER TERNARY LOGIC CIRCUIT
    Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
    US & KR (Registered)
  4. APPARATUS AND METHOD FOR TERNARY LOGIC SYNTHESIS WITH MODIFIED QUINE-MCCLUSKEY ALGORITHM
    Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang
    US & KR (Registered)

Skills

    Linux
    ― Server manager (CentOS, Ubuntu)
    Programming Language
    ― C/C++, Python, Tcl, Verilog
    Electronic Design Automation (EDA) Tools
    CADENCE
    ― Innovus, Virtuoso, Quantus, Genus, Xcelium, NC Verilog
    SYNOPSYS
    ― Design Compiler, IC Compiler II, StarRC, PrimeTime, Hspice
    ANSYS
    ― HFSS, SIwave, AEDT, RedHawk